Embedded Device Waveform EDSA Reference Information

Background

ISASecure EDSA requirements dictate that during testing, a DUT will output a specific electrical signal for each type of output. The timing accuracy of that signal’s transition will be monitored for critical degradations, as a means of confirming the validity of “essential downward services”.

There are three possible signals coming out from the DUT and/or its test-harness:

Electric digital, TTL level waveform with a period of 1s up, and 2s down.

NOTE: Transition timing jitters must be under the given maximum allowed (-mj) at least 95% of the samples, or at a higher percentage supplied by the vendor. To accommodate that, a new -mc (Minimum Confidence) parameter with a default/minimum of 0.95 was added. To reproduce the “old”, strict behaviour, set the value to 1. The percentage count restarts together with the tool restart, whether auto or manual.
Electric analog, 4-20mA signal (usually at “signal-level” voltages) waveform with a period of going up 10 x 1s at each range/10 level, then going down 20 x 1s at each range/20 level.

NOTE: In parallel with electric digital, all transition timing jitters must be smaller than: max_allowed_polling_lag + (1.5 * max_allowed_jitter). To accommodate that, a new –cj (“Composite Jitter” factor) parameter that factors that expression was added with a default of 1.0.
For signals that do not conform to the upper 2 groups, the DUT incorporates its own testharness that monitors those signals and switches the state of a digital out as a result.

The EDW monitor is NOT expected to monitor the voltage output accuracy of the digital (a) and analog (b) channels, and subsequently also not the “shape” of the analog waveform - but only their correct timing. Any transition with a timing jitter bigger than allowed, or a test-harness fault signal (c), will trigger an exception, register it in the log, and optionally reset the DUT.

However, the new EDSA-310-ERT.R30 calls for decreasing the max allowed polling lag (“measurement jitter”) from 100ms (10%) to 10ms (1%). Luckily, the new value was already the default since the first version (see -pl option). As well as adding three new pieces of information:

A transition in an Analog signal is considered to occur once the sampled voltage reaches at least 90% of its target value. For example, suppose our signal range is 0..5v. A step up from 0.5v to 1.0v would be already satisfied if the sampled value at the time of transition would be at least 0.95v (0.5 + (0.90 * 0.5)). A step down from 5v to 4.75v would be already satisfied if the sampled value at the time of transition would be at most 4.775v (5.0 - (0.90 * 0.25)). To accommodate that, a new -at (Analog Threshold) parameter with a default of 0.9 was added.